1. Field of the Invention
The present invention relates to a data storage apparatus and to a control method thereof.
2. Description of the Related Art
A method of reducing a drive frequency (or a control cycle) of a controller adapted to control a system, which includes a memory (for instance, a DRAM (Dynamic Random Access Memory)) serving as a data storage unit that stores data (see, for example, Japanese Patent Application Laid-Open No. 2002-7316), is known as a method of reducing the electric power consumption of the system. Also, a method of reducing the power consumption by inhibiting access to a memory through a bus comprising plural signal lines used for transmitting data to and for receiving data from the memory and by causing the memory to perform a self-refresh operation is known (see, for instance, Japanese Patent Application Laid-Open No. 2003-59266). Also, a method of holding data when interrupting power supply to a system, which includes a memory (for example, a DRAM) serving as a data storage unit that stores data, by causing the memory to perform a self-refresh operation and by supplying electric power to the memory from a backup auxiliary power supply is known (see, for example, Japanese Patent Application Laid-Open No. 7-334432). However, these conventional methods have the following drawbacks.
For instance, according to the method described in Japanese Patent Application Laid-Open No. 2002-7316, the drive frequencies of the memory itself and the controller, which controls the memory, are reduced to thereby decrease the power consumptions thereof. However, in a case where an intermediate voltage (for example, 1.25V) of a power supply voltage (for instance, 2.5V) for a memory system is supplied to the plural signal lines of the bus connecting the controller to the memory, even when the memory and the controller are not driven at the predetermined drive frequency, electric current can flow from the power supply, which supplies the intermediate voltage, to the plural signal lines, so that power consumption occurs corresponding to the electric current. Also, the power consumption depends upon the level of a voltage outputted from each of the plural control signal lines. For example, in a case the voltage of the all of the signal lines are set lower than the intermediate voltage, the electric current can flow from the power supply to the all of the signal lines. Incidentally, an SSTL2 (Stub Series Terminated Logic for 2.5V) interface employed in a DDR-SDRAM (Double Data Rate SDRAM) is known as an interface adapted to supply the intermediate voltage (for example, 1.25V) of the power supply voltage (for example, 2.5V) for the memory system.
According to the method described in Japanese Patent Application Laid-Open No. 2003-59266, the power consumption can be reduced by supplying electric power only to the memory. However, this method has a drawback in that it takes time to resume transmission/reception of data between the controller and the memory.
According to the method described in Japanese Patent Application Laid-Open No. 7-334432, electric current flowing into the bus from a buffer provided at an output terminal of the controller, from which data is outputted to the memory, can be reduced by causing the memory to perform a self-refresh operation, by also supplying electric power to the memory from the backup auxiliary power supply, and by putting the buffer into a high impedance state. However, this method has a drawback in that a data communication rate is lowered when the transmission and reception of data are performed through the bus, which comprises the plural signal lines, in a case of employing a method of inserting a resistor between a ground potential (GND) and the bus.